GlobalSpec

Appendix 1: CMOS Process Flow

Starting material p-type substrate or p epi on p + substrate for latch-up prevention (Taur et al., 1984). Grow pad oxide. Deposit CVD (Chemical Vapor Deposition) nitride. (See Fig. A1.1.) FIGURE A1.1 ...
Phys.org

Functional ring oscillators based on stacked gate-all-around silicon nanowire transistors

At this week's 2017 International Electron Devices Meeting (IEDM), imec, the research and innovation hub in nano-electronics and digital technology, reports on multiple key process optimizations for ...
EDN

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...
EDN

InGaP HBT vs CMOS for mobile handset power amplifiers

Designers of mobile handsets and wireless networking products know that the power amplifier (PA) is a make or break component in terms of performance, footprint, and battery life. Selecting the right ...
Design-Reuse

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...